In sample and hold circuits used in analog digital converters and the like, which handle high speed signals, a current switching source-follower type of sample and hold circuit is frequently used.
FIG. 6 shows a first conventional example of a current switching source-follower type of sample and hold circuit (refer to FIG. 8 etc. of Patent Document 2). This sample and hold circuit is configured from an input stage amplifier circuit 11 for amplifying a differential voltage of input signals IN and INB by a prescribed amplification rate, a current switching source-follower type of hold circuit 2 for holding an analog output voltage of the input stage amplifier circuit 11, and an output buffer 3 for buffering output of the hold circuit 2.
The input stage amplifier circuit 11 is provided with NMOS transistors Tr11 and Tr12, and resistor elements R11 to R14. The NMOS transistor Tr11 has a drain connected to a power supply VDD via the resistor element R11, a source connected to a power supply I11 via the resistor element R13, and a gate that is given the input signal IN. The NMOS transistor Tr12 has a drain connected to the power supply VDD via the resistor element R12, a source connected to the power supply I11 via the resistor element R14, and a gate that is given the input signal INB of a reverse phase to the input signal IN. This type of input stage amplifier circuit 11 is configured as an input stage differential amplifier circuit, and amplifies a differential voltage of the input signals IN and INB by a prescribed amplification rate, to be supplied to the hold circuit 2 as an output signal PREOUT from the drain of the NMOS transistor Tr12.
The hold circuit 2 is provided with NMOS transistors Tr3 to Tr5, a current source I2, and a capacitor CH for holding voltage. The NMOS transistor Tr3 has a drain connected to the power supply VDD, a source is connected to one end of the capacitor CH and a drain of the NMOS transistor Tr5, and a gate is given the output signal PREOUT. The NMOS transistor Tr4 has a drain connected to a gate of the NMOS transistor Tr3, a source is connected to a current source I2, and a gate is given a sampling clock signal CLKB. The NMOS-transistor Tr5 has a source connected to the current source I2, and a gate is given a sampling clock signal CLK of reverse phase to the sampling clock signal CLKB. In the capacitor CH, one end is given a hold signal VHOLD and another end is connected to ground.
An output buffer 3 is provided with a NMOS transistor Tr6 and a resistor element R5. The NMOS transistor Tr6 has a drain connected to the power supply VDD, an output signal OUT is outputted from a source, together with the source being connected to ground via the resistor element R5, and a gate is connected to the one end of the capacitor CH.
Operation of a sample and hold circuit is described making reference to a timing chart of FIG. 7. First, when the sampling clock signal CLK is at a HIGH level (CLKB is at a LOW level), the input stage amplifier circuit 11 operates simply as a linear amplifier circuit, and outputs a voltage proportional to differential voltage of the input voltages IN and INB as an output signal PREOUT. Furthermore, in the hold circuit 2, since a current from the current source I2 flows to the NMOS transistor Tr5 side, the NMOS transistor Tr3 operates as simply a source-follower, and while charging the capacitor CH, outputs a voltage in accordance with the output signal PREOUT, as a hold signal. VHOLD. The output buffer 3 receives the hold signal VHOLD at high impedance, and, as an output signal OUT, outputs a voltage according to the holding signal VHOLD as an output signal OUT. That is, when the sampling clock signal CLK is at a HIGH level (CLKB is at a LOW level), the sample and hold circuit performs a sample operation as simply an amplifier, and outputs the output signal OUT following an input signal.
On the other hand, when the sampling clock signal CLK is at a LOW level (CLKB is at a HIGH level), with the NMOS transistor Tr5 OFF, the current of the current source I2 flows in the resistor element R12 of the input stage amplifier circuit 11 of a front stage via the NMOS transistor Tr4. Therefore, with regard to the resistor element R12, a voltage drop of R12×I2 occurs at a connection point with a gate of the NMOS transistor Tr3, potential of the output signal PREOUT drops, and the NMOS transistor Tr3 is OFF. (Note that I2>I11 is necessary in order that Tr3 is not ON even if maximum input is applied. With this condition, with regard to the potential of the output signal PREOUT, Tr3 is always in an OFF state according to the voltage drop of R12×I2.) In this way, the capacitor CH is separated from the NMOS transistor Tr3. However, a charge immediately before the sampling clock signal CLK switches from a HIGH level to a LOW level, is held in the capacitor CH. Therefore, potential of the hold signal VHOLD is held, and a voltage at an instant at which the sampling clock signal changes from a HIGH level to a LOW level, is outputted from the output buffer 3 (hold operation).
In this way, the conventional sample and hold circuit operates as a simple amplifier when the sampling clock signal CLK has a HIGH level, and when the sampling clock signal CLK has a LOW level, operates as a hold circuit for holding the voltage at the instant the sampling clock signal CLK changes from a HIGH level to a LOW level.
However, in the first conventional example, the input stage amplifier circuit 11 operates during the hold period and causes the gate potential (PREOUT) of the NMOS transistor Tr3, which is a source follower of the hold circuit 2, to waver. As described above, normally, according to the current of the current source I2 flowing via the NMOS transistor Tr4 and the voltage drop due to the load resistor (R12) of the input stage amplifier circuit 11, the potential of the output signal PREOUT is set to be low so that the NMOS transistor Tr3 is OFF (I2>I11). As a result, the NMOS transistor Tr3 is always in an OFF state. However, since the wavering of the output signal PREOUT leaks into the hold signal VHOLD, due to parasitic capacitance between the gate and source of the NMOS transistor Tr3, and the hold signal VHOLD is varied, there has been a problem in that the input signal leaks (feeds through) to output.
As a means of solving this feed-through problem, a second conventional example shown in FIG. 8 is disclosed (refer to FIG. 2 etc. of Patent Document 1). In this conventional example, a current bypass circuit 5 is further provided, and by using a bypass transistor TrBp forming the current bypass circuit 5 during a hold period, a bias current (current of a current source I11) of the input stage amplifier circuit 11 is bypassed to the power supply VDD. By the bypass of the bias current (I11), the NMOS transistors Tr11 and Tr12 that form an input stage differential pair are OFF, and feed-through is suppressed by arranging such that an input signal is not transmitted to the hold circuit 2 of a subsequent stage.
Furthermore, as another means of suppressing feed-through, a third conventional example shown in FIG. 9 is disclosed (refer to FIG. 2 etc. of Patent Document 2). With regard to the sample and hold circuit of FIG. 6, a circuit in this case is further provided with a bias current switching circuit 14 having NMOS transistors Tr17 and Tr18 as a differential pair, and a constant voltage supply circuit 16 having NMOS transistors Tr9 and Tr10 as a differential pair. During a hold period, by the bias current switching circuit 14, a bias current (current of the current source I1) of the input stage amplifier circuit 11 is bypassed to the constant voltage supply circuit 16 to which a constant voltage (HIGH/LOW) is applied. By the bypass of the bias current, the feed-through is suppressed by supplying a constant voltage such that an NMOS transistor Tr3 is OFF, to the hold circuit 2.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-H09-130168A[Patent Document 2]    JP Patent Kokai Publication No. JP2006-157648A